Like many types of devices, it is easy to fall into the misconception that larger chips are better and more influential. However, when it comes to FPGAs (Field Programmable Gate Arrays), smaller chips often have the greatest application range and influence.
Small FPGAs are widely used in various devices, applications, and industries because they can reliably perform critical functions that are essential for the rapid operation of many different types of intelligent systems. At the same time, due to their programmable nature, they can be easily customized according to the specific requirements of different types of devices.
Lattice Semiconductor has been developing unique features of small FPGAs for many years and has built a business with an annual revenue of approximately $500 million around these features. Recently, the company has launched the second-generation version of its small FPGA architecture. The new Lattice Nexus™ 2 platform uses a 16nm TSMC FinFET process and has several important advantages brought by the smaller process node. In particular, compared with the products of other suppliers, chips based on Nexus 2 can operate at the best power and higher speed, and have a smaller physical size.
In addition, Lattice has integrated more and faster connection solutions and enhanced support for security standards in the Nexus 2 platform. In terms of connectivity, Nexus 2 supports multi-protocol 16G SERDES through the integration of PCIe Gen 4 controllers, and MIPI D and C-PHY speeds up to 7.98 Gbps. The platform also supports the use of high-speed LPDDR4 memory, thereby achieving faster overall system performance.
In terms of security, Nexus 2 supports 256-bit AES-GCM and SHA3-512 standards and complies with FIPS 140-3 Level 2 standards. All of this means that devices using this chip can have stronger security in sensitive and mission-critical environments. Moreover, since such FPGAs are typically used in devices with long lifespans, the Nexus 2 platform is prepared for the post-quantum era, greatly reducing the pressure on system designers as they know these devices can even handle potential security challenges in the future.
The first device in the Nexus 2 platform is the Lattice Certus™-N2 series of general-purpose FPGAs, and many of Lattice's customers have already received samples. Additionally, Lattice has upgraded its Lattice Propel and Lattice Radiant design software tools to support these new chips, making it easier for system designers to customize them according to their specific needs.
With these new features, the Certus-N2 chips will be able to provide higher performance in existing applications and offer a range of opportunities for new applications. For example, in practical applications, power consumption can be reduced by up to three times compared to similar products, meaning that the new devices consume less power, operate more reliably, and have longer operating times in battery-powered environments.
The performance improvements of the new platform are reflected in multiple aspects. Firstly, faster bandwidth connections between SERDES, DRAM, flash memory, and PCI enable the system to work more efficiently and connect with peripherals of higher data rates. This is also the key reason why the startup speed of Nexus 2 FPGAs is much faster (up to 20 times) than some competitors.
Since FPGAs typically play the role of an intermediary between sensors and computing and provide interconnection points in larger systems, these new features create opportunities for new applications. For example, in modern automotive designs with a partitioned architecture, fast and reliable interconnections are needed between these partitions. Additionally, when a car is in motion, Certus-N2 can wake up almost instantly and play a significant role in responding to external trigger data. In environments where high-speed motors are used to control robots (such as in manufacturing), similar applications also become possible.
Other major architectural advantages of the Nexus 2 include: the number of customizable logic units is twice that of the first-generation Nexus devices, and the number of DSP cores is more than three times that of the first generation, up to 520. These features combined can run more advanced algorithms, making it possible to improve the accuracy and speed of edge inference applications such as human or object presence detection, image or audio recognition, etc.
Although these applications may not receive as much attention as the latest GPUs today, the critical nature of the tasks handled by small FPGAs makes them an indispensable part of many devices today. Controlling the boot process, connecting sensors to the computing center, running time-sensitive dedicated algorithms, and more functions that small FPGAs can achieve, are all at the core of advanced system operation.
As today's advanced devices continue to use various advanced functions, the requirements for chips that support these basic operations are also constantly increasing. Therefore, enhancing the performance of the Nexus series of small FPGAs is an important and far-reaching step in powering the next generation of advanced systems.
(Reprinted from: Semiconductor Core Technology)